The present invention relates to a method of automatically assigning input/output pins of large scale integration (LSI) devices and modules in electronic apparatuses designed in a hierarchic fashion.
Conventionally, there has been known a pin assignment method as described in JP-A-59-197189 wherein in order to attain a satisfactory wiring efficiency, when assigning pins of signal lines to be connected from a lower-priority part to an external device by use of pins, those pins existing along connecting directions of the signal lines are selected for the pin assignment, thereby reducing the total length of signal lines.
In the prior art referred to above, however, consideration has not been given to attributes of signal lines to be assigned with the input/output pins, which leads to a problem of an occurrence of a signal delay defect or failure. Delay defects are considerably related to three cases as follows. In the first case, although bus lines corresponding to the respective bits of a register are desirably required to have a uniform delay time, because the respective pins are allocated to dispersed positions, the delay time has a large fluctuation. In the second case, when signal lines of a plurality of external gates connected to an identical internal gate of an LSI device are to be connected via output pins, the pins for the signal lines are required to be assigned to positions in the vicinity of an output gate so as to prevent the delay time in the LSI device from being remarkably increased. In the third case, the wiring order is required to be determined in consideration of delay time of a path including the signal lines to which pins are to be assigned. If the wiring order is arbitrarily determined, the pin assignment is delayed for signal lines included in a path having a smaller margin between the allowable delay time and the computed delay time such that some pins are assigned to be disadvantageously elongate wiring lengths between LSI devices and/or modules. In the description above, a path designates a closed wiring between flip-flop circuits.